Conventionally, a gaseous mixture of CF4, CHF3, O2 and Ar is used as an etching gas to plasma etch SiN (silicon nitride) layer and SiO2 (silicon oxide) layer, (see, e.g., Japanese Patent Laid-open Publication No. 1998-321597).
However, in case of plasma etching the SiN layer and the SiO2 layer by a gaseous mixture of CF4, CHF3, O2 and Ar via a mask to form a compact wiring portion and a loose wiring portion in the SiN layer and the SiO2 layer, a line width of wiring at the compact wiring portion and that at the loose wiring portion formed in the SiN layer and the SiO2 layer after etching become different, wherein the mask has a dense pattern portion corresponding to the compact wiring portion where the wiring of a desired target line width is arranged densely and a sparse pattern portion corresponding to the loose wiring portion where the wiring of a desired target line width is arranged sparsely. Moreover, such line widths are in a wide-range distribution, further exacerbating the problem of line width variations between the compact and the loose wiring portions after etching.
In general, a plurality of cells are arranged in a mesh pattern on the entire surface of the silicon wafer, wherein each cell is made up of a circuit pattern including the aforementioned compact wiring portion and loose wiring portion. Therefore, when etching is executed by a gaseous mixture of CF4, CHF3, O2 and Ar on such wafer, there occurs, for instance, the problem of an in-surface variation where the line width of a wiring at the compact wiring portion located in a center portion of the silicon wafer becomes different from that at a peripheral portion thereof.
The line width is becoming smaller due to a recent trend of miniaturization and high-integration of semiconductor devices. In order to fulfill such requirement of smaller line width, the line width of a wiring formed in an etched SiN layer and/or SiO2 layer may need to be made smaller than the line width of a pattern of a corresponding mask layer. In other words, the width of an opening formed in the etched layer may be made larger than that in the mask layer. Such etching is called trimming. During such a trimming process, the process conditions need to be adjusted to obtain a desired line width of a wiring in the etched layer. In the trimming process, it is required to prevent the occurrence of line width variations between a compact and a loose wiring portions and the in-surface variation.